verilog-sv-language
Pass
Audited by Gen Agent Trust Hub on Mar 16, 2026
Risk Level: SAFE
Full Analysis
- [SAFE]: The skill content is focused on technical hardware description language (HDL) development. The provided templates and instructions follow industry best practices for SystemVerilog-2017 design.
- [COMMAND_EXECUTION]: The skill uses the
Bashtool to interface with standard Electronic Design Automation (EDA) tools. The documented commands are for routine tasks such as linting, formatting, and compiling hardware designs using well-known open-source software like Verilator and Icarus Verilog. - [EXTERNAL_DOWNLOADS]: The skill contains references to documentation and standards from trusted organizations, including IEEE, Xilinx, and the Chips Alliance. No automated downloads of external scripts or executables from untrusted sources are present.
- [PROMPT_INJECTION]: No evidence of prompt injection patterns was found. The instructions do not attempt to bypass safety constraints or override the primary behavior of the agent.
- [DATA_EXFILTRATION]: The skill does not contain any patterns suggesting the exfiltration of sensitive data or unauthorized network communication.
Audit Metadata