rtl-equivalence-checker

BENIGN. The RTL Equivalence Checker analyzes two Verilog designs for functional equivalence, focusing on semantic vs cosmetic differences and providing counterexamples when non-equivalent. The described workflow uses local parsing and analysis scripts with standard file I/O and does not request or transmit credentials, nor does it rely on unverifiable binaries or external services. Overall, the footprint aligns with its stated purpose and remains proportionate and non-exfiltrating.