chip-design-engineer
Pass
Audited by Gen Agent Trust Hub on Mar 25, 2026
Risk Level: SAFE
Full Analysis
- [SAFE]: The skill provides expert guidance on RTL design, logic synthesis, and physical design flows using industry-standard EDA tools. No evidence of malicious behavior, data exfiltration, or prompt injection was found.
- [COMMAND_EXECUTION]: The skill includes numerous examples of TCL and SystemVerilog code. These are provided as educational templates and reference material for use within EDA tools (like Synopsys PrimeTime or Cadence Innovus) rather than commands for the agent to execute on the local system.
- [EXTERNAL_DOWNLOADS]: No remote download or execution patterns were detected. The skill mentions standard tools and the 'cocotb' Python package for verification, but does not attempt to install them at runtime.
- [PROMPT_INJECTION]: The system prompt and instructions follow established persona-setting guidelines without attempting to bypass safety filters or override core agent instructions.
Audit Metadata